1. Field of the Invention
The invention relates to a circuit configuration for synchronous clock generation of at least two clock signals.
In modern construction techniques, microcontrollers are distinguished by a modular construction. The various components are separated from one another as much as possible. Among other things, that affects the clock pulse and particularly the clock generation, since different turn-on and turn-off conditions apply, for instance, and therefore there is not merely one single-phase or multiphase clock system, but usually more than one of them, distributed in blocks, on the integrated circuit. However, with that kind of procedure, assurance must be provided that the individual clock systems will not shift unintentionally relative to one another, which is a phenomenon also known by the term "clock skewing".
Heretofore known clock generating circuits begin with a central single-phase clock pulse, which is derived more or less directly from the clock signal supplied to the chip. The signal is then split, and the resultant clock pulses are linked by combinatorial logic and finally fed to an output driver. Clock skewing is minimized by suitable dimensioning of the output drivers, which are adapted to the current or present capacitive load.
In Patent Abstracts of Japan, Section E, Vol. 13 (1989), No. 433 (E-824), JP-1-161912, a clock generating circuit is shown in which various circuit blocks each have one clock input buffer that furnishes clock signals for that circuit block. The clock input buffers are supplied with a common input clock signal. They have a time lag that is adjustable in each case through a shift register. The delay value that is adjustable through the shift registers can be supplied externally.
However, that kind of clock generation has several disadvantages. First, it is highly dependent on the dimensions of the output drivers, which can vary during manufacture if great process fluctuations occur. Second, it is not possible to control or monitor the clock skewing.